(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a tiny silicon nitride spacer by using a fully wet etching technology in order to provide an improved process window.
(2) Description of the Related Art
Process windows in forming nitride spacers are usually very tight, as is well known in the art. For example, process window, that is, time to etch nitride spacers for split-gate flash memory cells are on the order of a few seconds. This is because, in general, anisotropic dry etch is used, which is very fast. Especially when very small spacers are required for better performance of split-gate cells, a few seconds of etch time makes it very difficult to control the dimensions, let alone the shape of the spacers. A poorly defined spacer will cause, what is known in the art as “write disturb”, or, unwanted reverse tunneling, or erasing. Also, the endurance (the number of times the cell can be written and erased) is degraded as well as the erase and program (writing) speed of the cell. It is disclosed later in the embodiments of the present invention a method of opening up the etching process window from tens of seconds to several minutes with the attendant result of having much better controlled tiny silicon nitride spacers, and hence improved flash EPROM.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well-known split-gate cell is shown in FIG. 1. There, a MOS transistor is formed on a semiconductor substrate (10) having a first doped region (11), a second doped region (13), a channel region (15), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (15) have a first conductivity type, and the first (11) and second (13) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (11), lies within the substrate. The second doped region, (13), lies within substrate (10) and is spaced apart form the first doped region (11). Channel region (15) lies within substrate (10) and between first (11) and second (13) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
The programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (F-N) tunneling as is well known in prior art. Basically, a sufficiently high voltage is applied to the control gate and source while the drain is providing a constant flow of electrons in the channel region in the substrate. Some of these electrons gain enough energy to transfer from the substrate to the floating gate through the thin gate oxide layer by means of Fowler-Nordheim tunneling. The tunneling is achieved by raising the voltage level on the source to a sufficiently high value of about 12 volts so that the floating gate will couple to about 8 volts. As the electronic charge builds up on the floating gate, the electric field is reduced, which reduces the electron flow. When, finally, the high voltage is removed, the floating gate remains charged to a value lower than the threshold voltage of a logic high that would turn it off. Since tunneling process is reversible, the floating gate can be erased by raising the control gate voltage and grounding the drain and source voltage, thereby causing the stored charge on the floating gate to flow to the control gate by F-N tunneling. Of importance in the tunneling region is the quality and the thinness of the tunneling oxide separating the floating gate from the substrate. Inadvertent reverse tunneling, or erasure, for example, may occur if the tunnel oxide is degraded, or the spacer formed between the floating gate and the control gate is poorly shaped.
In prior art, spacers are formed in various, different ways. Hsieh, et al., in U.S. Pat. No. 6,174,772 describe forming nitride spacers in a split-gate flash memory cell. The nitride spacers are formed on a pad oxide prior to the forming of an intergate oxide layer. In this manner, any damage that would normally occur to the intergate oxide during the etching of the nitride spacers subsequent to the forming of the intergate oxide is avoided. Consequently, the variation in the thickness of the intergate oxide due to the unpredictable damage to the underlying spacers is also avoided by reversing the order in which the spacers and the intergate oxide are formed, including the forming of the pad oxide first.
In a different approach, Chien, et al., in U.S. Pat. No. 5,879,993 form a spacer structure adjacent to the sidewall of a floating gate electrode with a top surface and sidewalls, the floating gate electrode being formed on a silicon oxide dielectric layer, and the silicon oxide dielectric layer being formed on the top surface of a semiconductor substrate. The method includes the following steps: form a cap layer on the floating gate electrode, and a blanket tunnel oxide on the device; forming an inner dielectric, spacer layer over the device including the cap layer and the sidewalls thereby with conforming sidewalls, and an outer dielectric, spacer layer over the inner dielectric, spacer layer including the conforming sidewalls; etching partially the outer dielectric, spacer layer with a dry etch to form an outer dielectric spacer adjacent to the conforming sidewalls; partially etching more of the outer dielectric, spacer layer with a wet etch to expose a portion of the conforming sidewalls of the inner dielectric, spacer layer; etching the portion of the inner dielectric, spacer layer unprotected by the outer dielectric spacer before forming interelectrode dielectric layers and the control gate electrode.
Another method of forming spacers for flash EEPROM devices is disclosed by Chien, et al., in U.S. Pat. No. 6,001,690. A silicon nitride layer is formed over the floating gate in a memory cell. In one embodiment, a full isotropic/anisotropic etching of a particular recipe is performed on the nitride layer, while in a second embodiment a partial isotropic/anisotropic etching is followed by full anisotropic etching, using a different recipe.
In still another U.S. Pat. No. 6,069,042, Chien, et al., teach a method for forming a multi-layer spacer (MLS) for flash EPROM devices. A composite tetraethylorthosilicate-silicon nitride (TEOS/Si3N4) layer is deposited over the floating gate and anisotropically etched to form the MLS.
On the other hand, Lin, et al., provide a method for forming a split-gate flash memory cell in U.S. Pat. No. 6,046,086, where an extra thin nitride layer is formed over the primary gate oxide layer, while Ogura, in U.S. Pat. No. 6,074,914, teaches a method of fabricating an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate.
It is disclosed in the present invention a different method of forming a spacer in a split-gate flash memory cell where only isotropic wet etch is used.